Prior to leaving P_ON, the microcontroller must set the Atmel AT86RF232 pins to the
default operating values: pin 11 (SLP_TR) = L, pin 8 (/RST) = H and pin 23 (/SEL) = H.
All interrupts are disabled by default. Thus, interrupts for state transition control are to
be enabled first, for example enable IRQ_4 (AWAKE_END) to indicate a state transition
to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON
state. In P_ON state a first access to the radio transceiver registers is possible after a
default 1MHz master clock is provided at pin 17 (CLKM), refer to t TR1 to Table 7-1 .
Once the supply voltage has stabilized and the crystal oscillator has settled (see
parameter t XTAL refer to Table 7-2 ), a valid SPI write access to register bits TRX_CMD
(register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF
initiate a state change from P_ON towards TRX_OFF state, which is then indicated by
an interrupt IRQ_4 (AWAKE_END) if enabled.
7.1.2.2 SLEEP – Sleep State
In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating beyond
the circuitry monitoring pin 11 (SLP_TR) and pin 8 (/RST). This state can only be
entered from state TRX_OFF, by setting the SLP_TR = H.
If CLKM is enabled with a clock rates higher than 62.5kHz, the SLEEP state is entered
35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned
off. If the CLKM output is already turned off (register bits CLKM_CTRL = 0), the SLEEP
state is entered immediately. At clock rate 62.5kHz, the main clock at pin 17 (CLKM) is
turned off immediately.
Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP
state the radio transceiver register contents and the AES register contents remain valid
while the contents of the Frame Buffer are destroyed.
/RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby
sets all registers to their default values. Exceptions are register bits CLKM_CTRL
(register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for
details see Section 9.6.4 .
Note:
1.
If during SLEEP state a voltage jump on V DD occurs of more than 0.8V within
1ms, the internal Power-On logic detects this as a P_ON reset and the
AT86RF232 goes into the P_ON state.
7.1.2.3 TRX_OFF – Clock State
In TRX_OFF the crystal oscillator is running and the master clock is available if
enabled. The SPI interface and digital voltage regulator are enabled, thus the radio
transceiver registers, the Frame Buffer and security engine (AES) are accessible (see
Section 9.3 and Section 11.1 ).
In contrast to P_ON state the pull-up and pull-down configuration is disabled.
Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. The analog front-end
is disabled during TRX_OFF state.
Entering the TRX_OFF state from P_ON, SLEEP or RESET state is indicated by
interrupt IRQ_4 (AWAKE_END) if enabled.
7.1.2.4 PLL_ON – PLL State
Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator
(AVREG) first. After the voltage regulator has been settled, the PLL frequency
32
AT86RF232
8321A – MCU Wireless – 10/11
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